A micro-processor may include a processing pipeline to allow multiple instructions to be processed simultaneously. More particularly, a micro-processor may include an execution pipeline having multiple execution subunits to allow multiple instructions to be executed simultaneously. Due to this temporal overlap, data flow through a load/store portion (e.g., memory locations) of the execution pipeline may cause data dependences between some instructions.
In one example, data dependencies may be detected as early as a decode stage of the processing pipeline by a scheduler. Depending on when data is available in the load/store portion and when that data is needed for consumption in an execution subunit, the scheduler can send data from the load/store portion through a bypassing network to the execution subunit, or the scheduler can stall execution of the instruction until the data is available in the load/store portion. In either case, some time (e.g., one or more clock cycles) may pass while waiting for the data to become available for use in the load/store portion of the execution pipeline. Accordingly, in some cases, data may not be available for use as quickly as desired.